Re: MMDVM & UDRC

Annaliese McDermond
 

Thanks Johnathan. I’ll be working a things a bit today and this evening.

On Dec 8, 2018, at 12:36 PM, Jonathan Naylor via Groups.Io <naylorjs=yahoo.com@groups.io> wrote:

Hi Annaliese

I've done the changes to use a 48 kHz sample rate with the MMDVM-UDRC. I'm making no guarantees but the values are based on the working 48 kHz branch of the main MMDVM firmware. The only area that bothers me is the output level for POCSAG which may be very out compared to the others.
I’ll mainly be concentrating on D-STAR, YSF and DMR since that’s what I have test gear for.

This version should at least allow you to test with the UDRC and iron out any bugs.

I'd be very interested in any problems you find, and of course any pull requests that you may make to fix them.
I have a serial code fix for the read side of things. The transplanted MMDVMHost code has different semantics than the code for MMDVM-UDRC expects. The MMDVMHost code blocks when it receives an initial chunk of data and then waits indefinitely until it reads the entire buffer length requested. This doesn’t work for MMDVM-UDRC because it blocks the main event thread waiting for more serial data that will never come.

I did some significant remodeling of the serial input code so that it reads a little bit more judiciously and uses the length field of the MMDVM frame to figure out how much to ask the OS to read for it. This seems to solve the problem. I’ll PR it soon so you can at least take a look at it.

Remember that the DMR in this version is simplex only. Using the UDRC or similar hardware makes it impossible to have the type of synchronisation that duplex DMR repeating requires.
I understand the synchronization issues surrounding the DMR time slots. I’d like to get the rest of the protocols working correctly and then Bryan and I have had recurring ideas on how we could potentially deal with that issue. I’m curious, though, how tight is the timing issue time-wise. Does the PTT have to cycle in 1ms, 10ms, 100ms? I’m assuming it’s the time from the preamble in that slot to when actual data begins to flow.

Jonathan G4KLX
--
Annaliese McDermond (NH6Z)
Xenotropic Systems
mcdermj@...




On Friday, 7 December 2018, 10:18:47 GMT, Annaliese McDermond <nh6z@...> wrote:
On Dec 7, 2018, at 12:14 AM, Jonathan Naylor via Groups.Io <naylorjs=yahoo.com@groups.io> wrote:

Hi Annaliese

There are a set of filter coefficients for 48 kHz sample rate in a branch of the MMDVM firmware. I’ll look into slotting those in and altering the other variables.

Ideally I’d recalculate them in MATLAB as floating point but my license for it ran out. Octave can probably do it though. Even rescaling from Q15 format will probably give enough precision.
If you have some matlab code, I have a Matlab 2015b license on my Mac that I could spit out the coefficients for you. I’m mildly familiar with the process because I’ve done it for filter coefficients in the OpenHPSDR FPGA code that I was playing with.


It’s bizarre seeing Linux kernel AX25 being mentioned. I wrote that stuff 23 years ago and last looked at it 20 years ago. I’m not sure I could add anything to that discussion these days.

Jonathan G4KLX
--
Annaliese McDermond (NH6Z)
nh6z@...



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